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low power , 165 mhz hdmi receiver data sheet ADV7610 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices . trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features high - definition multimedia interface (hdmi ? ) all m andatory and additional 3d video formats supported extended colorimetry, including sycc601, adobe rgb, adobe ycc 601, and xvycc extended gamut color cec 1.4 - compatible hdmi receiver 165 mhz maxi mu m transition - minimized differential signaling ( tmds ) clock frequency 24- bit output pixel bus high - bandwidth digital content protection (hdcp) 1.4 support with internal high definition copy protocol ( hdcp ) keys hdcp repeater support : u p to 127 ksvs support ed integrated consumer electronics control ( cec ) controller programmable hdmi equalizer 5 v d etect and hot plug ? a ssert for hdmi port audio support s/pdif (iec 60958 - compatible) digital audio hdmi audio extraction support advanced audio mute feature i 2 s , 4 streams for 8 channels general interrupt controller with two interrupt outputs standard i dentification (stdi) circuit highly flexible 24 - bit pixel output interface internal extended display identification data ( edid ) ram any - to - any 3 3 color space conve rsion (csc) matrix 2 - layer printed circuit board ( pcb ) design supported 76- ball , 6 mm 6 mm, chip - scale package bga applications portable applications pico p rojectors digital video cameras functional block dia gram hs/vs 4 i 2 s s/pdif hdcp keys tmds ddc hdmi1 deep color hdmi rx ADV7610 component processor 36 output mux field/de llc data mclk sclk lrclk lrclk i 2 s mclk sclk output mux 24-bit ycbcr/rgb hs vs/field de llc 10775-001 figure 1.
ADV7610 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diag ram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 detailed function al block diagram .......................................... 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 data and i 2 c timing characteristics ......................................... 5 absolute maximum ratings ............................................................ 7 package thermal performance ................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 power supply sequencing ............................................................. 10 power - up sequence ................................................................... 10 power - down sequence .............................................................. 10 functional overview ...................................................................... 11 hdmi receiver ........................................................................... 11 component processor (cp) ...................................................... 11 other features ............................................................................ 11 pixel input/output formatting .................................................... 12 pixel data output modes features .......................................... 12 ou tline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 12/12 revision 0: initial version
data sheet ADV7610 rev. 0 | page 3 of 16 general description the ADV7610 is offered in professional (no hdcp) and industrial versions. the operating temperature range is ? 40 c to +85 c. the ADV7610 is a high quality, single input hdmi - capable receiver. it incorporate s an hdmi - capable receiver that supports all mandatory 3d tv defined in hdmi s pecification . the ADV7610 supports formats up to uxga 60 hz at eight bit s. it integrates a cec controller that supports the c apabi lity discovery and c ontrol (cdc) feature. the ADV7610 has a 4 - channel stereo audio output port for the audio data extracted from the hdmi stream. the hdmi receiver has an advanced mute controller that prevents audible extraneous noise in the audio output. the following audio formats are accessible: ? four stream s from the i 2 s serializer ( eight channels ) ? a stream from the s/pdif serializer (two uncompressed channels or n compressed channels, for example, ac3) ? a d st stream the hdmi port has dedicated 5 v d etect and hot plug a ssert pins. the hdmi receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cables. the adv76 10 contains one main component processor (cp) that processes the video signals from the hdmi receiver. it provides features such as contrast, brightness , saturation adjustments , stdi detection block , free run , and synchronization alignment controls. fabr icated in an advanced cmos process, the ADV7610 is provided in a 6 mm 6 mm, 76 - ball csp _ bga , rohs - compliant package and is specified over the ? 40c to +85 c tempera ture range. detailed functional block diagram control interface i 2 c control and data pll edid repeater controller hdcp engine packet/ infoframe memory 12 12 12 backend colorspace conversion o u t p u t f o r m a t t e r component processor 5v detect and hpd controller audio processor data preprocesor and color- space conversion hdmi processor packet processor a b c mute interrupt controller (int1, int2) p0 to p7 *int2 can be output on one of the following pins only: sclk/int2, mclk/int2, or hpa_a/int2. xtalp xtaln scl sda cec rxa_5v hpa_a/int2* ddca_sda ddca_scl rxa_c rxa_0 rxa_1 rxa_2 p8 to p15 p16 to p23 llc hs vs/field/alsb de int1 int2* lrclk sclk/int2* mclk/int2* 4 i2s0 to i2s3 audio output formatter hdcp eeprom sampler equalizer dpll cec controller ADV7610 10775-002 figure 2 . detailed functional block diagram
ADV7610 data sheet rev. 0 | page 4 of 16 specifications dvdd = 1.71 v to 1.89 v, dvddio = 3.14 v to 3.46 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.14 v t o 3.46 v, cvdd = 1.71 v to 1.89 v , t min to t max = ? 40c to +85c, unless otherwise noted. electrical character istics table 1 . parameter symbol test conditions /comments min typ max unit digital inputs 1 input high voltage v ih xtaln and xtalp 1.2 v v ih other digital inputs 2 v input low voltage v il xtaln and xtalp 0.4 v v il other digital inputs 0.8 v input current i in reset pin 45 60 a other digital inputs 10 a input capacitance c in 10 pf digital inputs (5 v tolerant) 1 , 2 input high voltage v ih 2.6 v input low voltage v il 0.8 v input current i in ?82 +82 a digital outputs 1 output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance leakage current i leak vs / field/alsb pin 35 60 a hpa _a /int 2 pin 82 a other 10 a output c apacitance c out 20 pf power requirements 3 digital core power supply dvdd 1.71 1.8 1.89 v digital i/o power supply dvddio 3.14 3.3 3.46 v pll power supply pvdd 1.71 1.8 1.89 v terminator power supply tvdd 3.14 3.3 3.46 v comparator power supply cvdd 1.71 1.8 1.89 v digital core supply current i dvdd uxga 60 hz at eight bit s 95.7 188.1 ma digital i/o supply current i dvddio uxga 60 hz at eight bits 12.9 178.5 ma pll supply current i pvdd uxga 60 hz at eight bits 30.7 36.9 ma terminator supply current i tvdd uxga 60 hz at eight bits 50.9 57.6 ma comparator supply current i cvdd uxga 60 hz at eight bits 95.8 114.4 ma p ower - down c urrents 4 digital core supply current i dvdd _pd power - down mode 1 0.2 0.5 ma digital i/o supply curren t i dvddio _pd power - down mode 1 1.3 1.7 ma pll supply current i pvdd _pd power - down mode 1 1.5 1.8 ma terminator supply current i tvdd _pd power - down mode 1 0.1 0.3 ma comparator supply current i cvdd _pd power - down mode 1 1.3 1.7 ma power - up time t pwrup 25 ms 1 data guaranteed by characterization . 2 the following pins are 5 v tolerant: ddc a _scl, ddc a _sda , and rx a _5v. 3 maximum current consumption values are recorded with maximum rated voltage supply levels, moire x video pattern, a nd at maximum rated temperature. 4 power - down mode 0 (i / o m ap , r eg ister 0x0c = 0x62), ring o sci llator powered down (hdmi m ap, r eg ister 0x48 = 0x01) , and ddc p ads off (hdmi m ap, r eg ister 0x73 = 0x01) .
data sheet ADV7610 rev. 0 | page 5 of 16 data and i 2 c timing characteris tics table 2 . parameter symbol test conditions/comments min typ max unit clock and crystal crystal frequency, xtal p 28.63636 mhz crystal frequency stability 50 ppm l lc frequency range 1 13.5 165 mhz i 2 c ports scl frequency 400 khz scl minimum pulse width high 2 t 1 600 ns scl minimum pulse width low 2 t 2 1.3 s start condition hold time 2 t 3 600 ns start condition setup time 2 t 4 600 ns sda setup time 2 t 5 100 ns scl and sda rise time 2 t 6 300 ns scl and sda fall time 2 t 7 300 ns stop condition setup time 2 t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc mark : space ratio 2 t 9 :t 10 45:55 55:45 % duty cycle data and control outputs 3 data output transition time 2 , 4 t 11 end of valid data to negative clock edge 1.0 2.2 ns t 12 negative clock edge to start of valid data 0.0 0.3 ns i 2 s port, master mode sclk mark : space ratio 2 t 15 :t 16 45:55 55:45 % duty cycle lrclk data transition time 2 t 17 end of valid data to negative sclk edge 10 ns lrclk data transition time 2 t 18 negative sclk edge to start of valid data 10 ns i 2 s data transition time 2 t 19 end of valid data to negative sclk edge 5 ns i 2 s data transition ti me 2 t 20 negative sclk edge to start of valid data 5 ns 1 maximum llc frequency is limited by the clo ck frequency of uxga 60 hz at eight bit s . 2 data guaranteed by characterization. 3 with the dll block on the output clock bypassed. 4 dll bypassed on the clock path.
ADV7610 data sheet rev. 0 | page 6 of 16 timing diagrams sda scl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 10775-003 figure 3. i 2 c timing t 9 llc t 11 t 12 t 10 p0 to p23, hs, vs/field/alsb, de 10775-004 figure 4 . pixel port and control sdr output timing sclk lrclk i 2 s left-justified mode i 2 s right-justified mode i 2 s i 2 s mode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 10775-005 fig ure 5. i 2 s timing
data sheet ADV7610 rev. 0 | page 7 of 16 absolute maximum rat ings table 3 . parameter rating dvdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v cvdd to gnd 2.2 v tvdd to gnd 4.0 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v 5 v tolerant digital inputs to gnd 1 5.3 v digital outputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v x talp, x taln gnd ? 0.3 v to pvdd + 0.3 v scl/sda data pins to dvddio dvddio ? 0.3 v to dvddio + 3.6 v maximum junction temp erature (t j max ) 125 c storage temperature range ? 60 c to + 150 c infrared reflow soldering (20 sec) 260 c 1 the following inputs are 3.3 v inputs but are 5 v tolerant: ddc a _scl , ddc a _sda , and rxa_5v . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal perf ormance to reduce power consumption when using the ADV7610 , turn off the unused sections of the part. due to the pcb metal variation and , therefore , variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because th is eliminates the variance associated with the ja value. do not exceed t he maximum junction temperature (t j max ) of 125c. the following equation calculates the junction tempera ture using the measured package surface temperature , and it applies only when a heat sink is not used on the device under test (dut): t j = t s + ( jt w total ) where: t s is the package surface temperature (c). jt = 0.4c/w for the 76- ball csp _ bga . w total = (( pvdd i pvdd ) + (0.05 tvdd i tvdd ) + ( cvdd i cvdd ) + ( dvdd i dvdd ) + ( dvddio i dvddio )) where 0.05 is 5% of the tvdd power that is dissipated on the device itself. esd caution
ADV7610 data sheet rev. 0 | page 8 of 16 pin configuration an d function descripti ons a b c d e f g j h k 1 3 4 5 8 9 10 2 6 7 hpa_a/ int2 ddca_scl pvdd xtaln mclk/ int2 sclk/ int2 dvdd rxa_5v xtalp int1 tvdd ddca_sda cec cs scl lrclk dvdd tvdd reset sda rxa_c+ i2s3 i2s1 rxa_c? rxa_0+ gnd gnd i2s2 i2s0 rxa_0? gnd dvdd rxa_1+ gnd vs/ field/ alsb de rxa_1? dvdd rxa_2+ gnd hs p0 rxa_2? dvddio cvdd gnd gnd p1 p2 cvdd gnd dvddio p23 p3 p4 p22 p21 p16 p15 p13 p7 p5 dvddio p18 p11 p9 p20 p17 llc p14 p8 p6 dvddio p19 p12 p10 10775-006 figure 6 . pin configuration table 4 . pin function descriptions ball no. mnemonic type description d4, d5, d6, e4, f4, g4, g5 , g6 gnd ground ground. a 1 hpa_a/int2 miscellaneous digital a dual function pin that can be configured to output a hot plug a ssert signal (for hdmi p ort a) or an interrup t 2 signal. g1, g 2 cvdd power hdmi analog block supply voltage (1.8 v). b1, b 2 tvdd power terminator supply voltage (3.3 v). f7, g7, j10, k10 dvddio power digital i/o supply voltage (3.3 v). a10, b10, d7, e7 dvdd power digital core supply voltage (1.8 v). a4 pvdd power pll supply voltage (1.8 v). c 2 rxa _c? hdmi input digital input clock complement of port a in the hdmi interface. c 1 rxa_c+ hdmi input digital input clock true of port a in the hdmi interface. d 2 rxa_0? hdmi input digital input channel 0 complement of port a in the hdmi interface. d 1 rx a_0+ hdmi input digital input channel 0 true of port a in the hdmi interface. e 2 rxa_1? hdmi input digital input channel 1 complement of port a in the hdmi interface. e 1 rxa_1+ hdmi input digital input channel 1 true of port a in the hdmi interface. f 2 rxa_2? hdmi input digital input channel 2 complement of port a in the hdmi interface. f 1 rxa_2+ hdmi input digital input channel 2 true of port a in the hdmi interface.
data sheet ADV7610 rev. 0 | page 9 of 16 ball no. mnemonic type description h 1 p23 digital video output video pixel output port. h 2 p22 digital video output vid eo pixel output port. j1 p21 digital video output video pixel output port. k 1 p20 digital video output video pixel output port. k2 p19 digital video output video pixel output port. j2 p18 digital video output video pixel output port. k3 p17 digital vi deo output video pixel output port. j3 p16 digital video output video pixel output port. k4 llc digital video output line locked output clock for the pixel data the range is 13.5 mhz to 162.5 mhz. j4 p15 digital video output video pixel output port. k5 p14 digital video output video pixel output port. j5 p13 digital video output video pixel output port. k6 p12 digital video output video pixel output port. j6 p11 digital video output video pixel output port. k 7 p10 digital video output video pixel ou tput port. j 7 p9 digital video output video pixel output port. k8 p8 digital video output video pixel output port. j8 p7 digital video output video pixel output port. k 9 p6 digital video output video pixel output port. j9 p5 digital video output video pixel output port. h10 p4 digital video output video pixel output port. h9 p3 digital video output video pixel output port. g10 p2 digital video output video pixel output port. g9 p1 digital video output video pixel output port. f10 p0 digital video output video pixel output port. e 10 de miscellaneous digital data enable . de is a signal that indicates active pixel data. f9 hs digital video output horizontal synchronization output signal . e 9 vs/field/alsb digital input/output vertical synchronizati on output signal . field synchronization output signal in all interlaced video modes. vs or field can be configured for this pin. the alsb allows selection of the i 2 c address. d10, c10 , d9, c 9 i2s 0 to i2s3 miscellaneous digital audio output pi n s . these pins can be configured to output s/pdif digital audio (s/pdif) or i 2 s. a 9 sclk/int2 miscellaneous digital a dual function pin that can be configured to output an audio serial clock or an interrupt 2 signal. b 9 lrclk miscellaneous digital audio left/right clock. a8 mclk/int2 miscellaneous digital a dual function pin that can be configured to output an audio master clock or an interrupt 2 signal. b8 scl miscellaneous digital i 2 c port serial clock input. scl is the clock line for the control po rt. b7 sda miscellaneous digital i 2 c port serial data input/output pin. sda is the data line for the control port. a7 int1 miscellaneous digital interrupt 1 . this pin can be active low or active high. when status bits change, this pin is triggered. the e vents that trigger an interrupt are under user configuration. b 6 reset miscellaneous digital system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the ADV7610 circuitry. a 6 x talp miscellaneous analog input pin for 28.63636 mhz crystal or an external 1.8 v, 28.63636 mhz clock oscillator source to clock the ADV7610 . a 5 x taln miscellaneous analog crystal inp ut. input pin for 28.63636 mhz crystal. b4 cec digital input/output consumer electronic control channel. b5 c s miscellaneous digital chip select (bar). pulling this line high cause s the i 2 c state machine to ignore the i 2 c transmission . a3 ddca_scl hdmi input hdcp slave serial clock port a. ddca_scl is a 3.3 v input that is 5 v tolerant. b 3 ddca_sda hdmi input hdcp slave serial data port a. ddca_sda is a 3.3 v input that is 5 v tolerant. a 2 rxa_5v hdmi input 5 v detect pin for port a in the hdmi interface.
ADV7610 data sheet rev. 0 | page 10 of 16 power supply sequenc ing power - up sequence the recommended power - up sequence of the ADV7610 is to power up the 3.3 v supplies first, followed by the 1.8 v supplies. hold r eset low whi le the supplies are powered up. alternatively, the ADV7610 can be powered up by asserting all supplies simultaneously. in this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not rise above a higher rated supply level. power - down sequence the ADV7610 supplies can be deasserted simultaneously as long as a higher rated supply does not fall below a lower rated supply. 3.3v power supply (v) 1.8v 3.3v supplies 1.8v supplies 1.8v supplies power-up 3.3v supplies power-up 10775-007 figure 7 . recommended power- up sequence
data sheet ADV7610 rev. 0 | page 11 of 16 functional overview hdmi receiver the receiver supports all mandatory and many optional 3d formats. it supports hdtv formats up to uxga at eight bit s. the hdmi - compatible recei ver on the ADV7610 incorporates programmable equalization of the hdmi data signals. this equalization compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths an d higher frequencies. it is capable of equalizing for cable lengths of up to 30 meters to achieve robust receiver performance. with the inclusion of hdcp, displays can receive encrypted video content. the hdmi interface of the ADV7610 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the hdcp 1.4 protocol. the ADV7610 has a synchronization regeneration block to regenerate the de based on the measurement of t he video format being displayed and to filter the horizontal and vertical synchronization signals to prevent glitches. the hdmi receiver also sup ports terc4 error detection for detection of corrupted hdmi packets following a cable disconnect. the hdmi receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. o n detection of these conditions, the audio signal can be ramped to prevent audio clicks or pops. audio output can be formatted to lpcm and iec 61937. the hdmi receiver features include: ? 162.5 mhz (uxga at eight bit s ) maximum tmds clock frequency ? 3d format support defined in the hdmi specification ? integrated equalizer for cable lengths of up to 30 meters ? hdcp 1.4 ? internal hdcp keys ? pcm audio packet support ? tdm i 2 s audio packet support ? repeater support ? internal edid ram ? hot plug a ssert output pin for an hdm i port ? cec controller component processor (cp) the ADV7610 has an any - to - any 3 3 csc matrix. the csc block is placed in the output section of the component processor . the c sc enables yprpb - to - rgb and rgb - to - ycrcb conversions . many other standards of colorspace can be implemented using the colorspace converter. cp features include: ? 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and other formats ? manual adjustments including gain (contrast) and offset (brightness ), hue, and saturation ? free run output mode that provides stable timing when no video input is present ? 162.5 mhz processing rate ? contrast, brightness, hue, and saturation controls ? standard identification enabled by stdi block ? rgb that can be color space c onverted to ycrcb and decima ted to a 4:2:2 format for video centric back - end ic interfacing ? de output signal supplied for direct connection to an hdmi/dvi transmitter other features the ADV7610 has hs, vs , fiel d , and de output signals with programmable position, polarity, and width. the ADV7610 has programmable interrupt request output pins, including int1 and int2 (int2 is accessible only via one of following pins : mclk/int2 , sclk/int2 , or hpa_a/int2) . it also features a low power - down mode. the i 2 c address of t he main map is 0x98 after reset. this can be changed after reset to 0x9a if pull - up is attached to the vs/field/alsb pin and the i 2 c command sample_alsb is issued. the ADV7610 is provided in a 6 mm 6 mm , rohs - compliant bga package and is specified over the ? 40c to +85c temperature range. for more detailed product information about the ADV7610 , contact the local analog devices, inc., sales office.
ADV7610 data sheet rev. 0 | page 12 of 16 pixel input/output f ormatting the output section of the ADV7610 is highly flexible. the pixel output bus can support up to 24 - bit 4:4:4 ycrcb. the pixel data supports both single data rate mode and double data rate mode. in sdr mode , a 16 - /24 - bit 4:2:2 or 24 - bit 4:4:4 output is possible. in ddr mode, the pixel output port can be configured in an 8 - /12 - bit 4:2:2 ycrcb or 24 - bit 4:4:4 rgb. bus rotation is supported. table 5 and table 6 outline the various output for mats that are supported. all output modes are controlled via i 2 c. pixel data output mo des features the output pixel port features include : ? 8 - /12 - bit itu - r bt.656 4:2:2 ycrcb with embedded time codes and/or hs, vs , and field output signals ? 16- /24 - bit ycrcb with embedded time codes and/or hs and vs/field pin timing ? 24- bit ycrcb/rgb with embedded time codes and/or hs and vs/field pin timing ? ddr 8 - /12 - bit 4:2: 2 ycrcb ? ddr 24 - bit 4:4:4 rgb table 5 . sdr 4:2:2 and 4:4:4 output modes sdr 4:2:2 sdr 4:4:4 op_format_sel[7:0] 0x0 0x0a 0x80 0x8a 0x40 pixel output 8 - bit sdr itu - r bt.656 mode 0 12- bit sdr itu - r bt.656 mode 2 16- bit sdr itu - r bt.656 4:2:2 mode 0 24- bit sdr itu - r bt.656 4:2:2 mode 2 24- bit sdr 4:4:4 mode 0 p23 high -z y3, cb3, cr3 high -z y3 r7 p22 high -z y2, cb2, cr2 high -z y2 r6 p21 high -z y1, cb1, cr1 high -z y1 r5 p20 high -z y0, cb0, cr0 high -z y0 r4 p19 high -z high -z high -z cb3, cr3 r3 p18 high -z high -z high -z cb2, cr2 r2 p17 high -z high -z high -z cb1, cr1 r1 p 16 high - z high - z high - z cb0, cr0 r0 p15 y7, cb7, cr7 y11, cb11, cr11 y7 y11 g7 p14 y6, cb6, cr6 y10, cb10, cr10 y6 y10 g6 p13 y5, cb5, cr5 y9, cb9, cr9 y5 y9 g5 p12 y4, cb4, cr4 y8, cb8, cr8 y4 y8 g4 p11 y3, cb3, cr3 y7, cb7, cr7 y3 y7 g3 p10 y2, cb2 , cr2 y6, cb6, cr6 y2 y6 g2 p9 y1, cb1, cr1 y5, cb5, cr5 y1 y5 g1 p8 y0, cb0, cr0 y4, cb4, cr4 y0 y4 g0 p7 high -z high -z cb7, cr7 cb11, cr11 b7 p6 high -z high -z cb6, cr6 cb10, cr10 b6 p5 high -z high -z cb5, cr5 cb9, cr9 b5 p4 high -z high -z cb4, cr4 cb 8, cr8 b4 p3 high -z high -z cb3, cr3 cb7, cr7 b3 p2 high -z high -z cb2, cr2 cb6, cr6 b2 p1 high -z high -z cb1, cr1 cb5, cr5 b1 p0 high -z high -z cb0, cr0 cb4, cr4 b0
data sheet ADV7610 rev. 0 | page 13 of 16 table 6 . ddr 4:2:2 and 4:4:4 output modes ddr 4:2:2 mode (cloc k/2) ddr 4:2:2 mode (clock/2) ddr 4:4:4 mode (clock/2) 1 , 2 op_format_sel[7:0] 0x20 0x2a 0x60 8 - bit ddr itu - 656 (clock/2 output) 4:2:2 mode 0 12- bit ddr itu - 656 (clock/2 output) 4:2:2 mode 2 24- bit ddr rgb (clock/2 output) pixel output clock rise clo ck fall clock rise clock fall clock rise clock fall p23 high -z high -z cb3, cr3 y3 r7 -0 r7 -1 p22 high -z high -z cb2, cr2 y2 r6 -0 r6 -1 p21 high -z high -z cb1, cr1 y1 r5 -0 r5 -1 p20 high -z high -z cb0, cr0 y0 r4 -0 r4 -1 p19 high -z high -z high -z high -z r3 -0 r3 -1 p18 high -z high -z high -z high -z r2 -0 r2 -1 p17 high -z high -z high -z high -z r1 -0 r1 -1 p16 high -z high -z high -z high -z r0 -0 r0 -1 p15 cb7, cr7 y7 cb11, cr11 y11 g7-0 g7-1 p14 cb6, cr6 y6 cb12, cr12 y12 g6-0 g6-1 p13 cb5, cr5 y5 cb9, cr9 y9 g5 - 0 g5 - 1 p12 cb4, cr4 y4 cb8, cr8 y8 g4-0 g4-1 p11 cb3, cr3 y3 cb7, cr7 y7 g3-0 g3-1 p10 cb2, cr2 y2 cb6, cr6 y6 g2-0 g2-1 p9 cb1, cr1 y1 cb5, cr5 y5 g1-0 g1-1 p8 cb0, cr0 y0 cb4, cr4 y4 g0-0 g0-1 p7 high - z high - z high - z high - z b7 - 0 b7 - 1 p6 high -z high -z high -z high -z b6 -0 b6 -1 p5 high -z high -z high -z high -z b5 -0 b5 -1 p4 high -z high -z high -z high -z b4 -0 b4 -1 p3 high -z high -z high -z high -z b3 -0 b3 -1 p2 high -z high -z high -z high -z b2 -0 b2 -1 p1 high -z high -z high -z high -z b1 -0 b1 -1 p0 high -z high -z high -z high -z b0 -0 b0 -1 1 - 0 = even samples. 2 - 1 = odd samples.
ADV7610 data sheet rev. 0 | page 14 of 16 outline dimensions * compliant t o jedec s t andards mo-225 with the exception to package height. a b c d e f g j h k 10 8 7 6 3 2 1 9 5 4 a1 corner index area top view ball a1 pad corner detail a bottom view 0.75 ref 6.10 6.00 sq 5.90 seating plane ball diameter 0.15 min 0.35 0.30 0.25 coplanarity 0.08 max 0.65 min 0.50 bsc 4.50 bsc sq * 1.40 max 010807- a de t ai l a figure 8. 76 - ball chip scale package ball grid array [csp _ bga ] (bc - 76 - 1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adv76 10bbcz ?40c to +85c 76- ball chip scale package ball grid array [csp _ bga] bc -76-1 ADV7610bbcz -rl ?40c to +85c 76- ball chip scale package ball grid array [csp _ bga], 13 tape and reel bc -76-1 ADV7610bbcz -p ?40c to +85c 76- ball chip scale package ball grid ar ray [csp _ bga], nonhdcp version bc -76-1 ADV7610bbcz - p - rl ?40c to +85c 76 - ball chip scale package ball grid array [csp _ bga], 13 tape and reel, nonhdcp version bc -76-1 1 z = rohs compliant part.
data sheet ADV7610 rev. 0 | page 15 of 16 notes
ADV7610 data sheet rev. 0 | page 16 of 16 notes the terms hdmi and hdmi high - definiti on multimedia interface, and the hdmi logo are trademarks or registered trademarks of hdmi licensing llc in the united states and other countries. ? 2012 analog devices, inc. all rights reserved. trademarks an d registered trademarks are the property of their respective owners. d10775 - 0- 12/12(0)

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